Charge coupled devices (hereinafter also referred to as CCD's) have found wide acceptance as shift registers for transporting charge in semiconductive substrates. A series of laterally spaced gate electrodes adjacent to but conductively separated from the semiconductive substrate and from one another are relied upon to transport minority carrier charge in discrete transfer steps within the semiconductive substrate. Each charge transfer step is achieved by proper potential biasing of the gate electrodes so that charge is attracted from one charge storage region to a next adjacent charge storage region in the semiconductive substrate.
It is essential that charge transfer be complete (high charge transfer efficiency) due to the large number, typically a thousand, of charge transfers employed in device operation. It is also desirable for some devices, such as full frame devices, that as much light as possible penetrate the electrode structure in regions where photosensitivity is desired.
Three phase CCD's, such as those described in Kahng et al., U.S. Pat. No. 3,700,932, are among the simplest to construct. The potential well in the substrate is uniform under each electrode and is controlled by the potential applied to the corresponding electrode. Charge transfer efficiency in three phase CCD's can be high because the potential in the semiconductive substrate varies monotonically from its value in the region under one electrode to that under an adjacent electrode when the two electrodes are biased for charge transfer, as is well known in the art. While three phase CCD's are simple in construction, the three phase clocking required for charge transport has been regarded as disadvantageous and the art has sought to construct a CCD capable of being driven by a two phase clock, in which case the CCD must be modified in construction to directionally bias charge transfer. An early two phase CCD, such as described in Kahng et al., U.S. Pat. No. 3,651,349, relied upon an insulator of stepped thickness under a single gate electrode to accomplish this modification, the step creating a region of lesser potential depth in the semiconductive substrate where the insulator was thinner and a region of greater potential depth where the insulator was thicker. Although the charge transfer efficiency of this device was high, the non-uniformity of the insulative layer was cumbersome to construct and required portions of the gate electrodes to lie in different planes, also complicating fabrication.
The art has therefore shown a preference for two phase CCD's having a simpler insulative layer and gate electrode construction relying on regions of increased impurity dopant concentration in the semiconductive substrate for directional biasing of charge transfer, as illustrated by Krambeck, U.S. Pat. No. 3,789,267. Such CCD's are illustrated by FIG. 1 in which a semiconductive substrate 301 of a first conductivity type supports an insulative layer 303 on which interlaid sets of gate electrodes 305,306, and 307 connected to the phase 1 and phase 2 power sources as shown are positioned. As shown, regions 309, formed by ion implantation in the semiconductive substrate, exhibit a different net level of impurity doping than the surrounding portions of the semiconductive substrate. The regions can be of the first conductivity type as taught in U.S. Pat. No. 3,789,267 or can alternatively be of a second conductivity type, as taught by Tasch et al. in U.S. Pat. No. 4,035,906. It is particularly preferred that such implants be of a species such as arsenic which diffuses only slowly in the semiconductive substrate, because thermal diffusion of dopants produces potential "wells" or potential "barriers" which trap charge during transfer, as is well known in the art. It is also preferred that such implants be accomplished at the lowest possible energies to reduce lateral spread or straggle of the dopant due to scattering of energetic dopant ions from the atoms in the substrate.
While the methods taught by U.S. Pat. Nos. 3,789,267 and 4,035,906 allow the use of low energy implants and of arsenic implants in particular, the implants and the gates are located with respect to one another by benchmarks not identified and are not self-aligned, as illustrated for a typical misalignment in FIG. 1. The art has encountered difficulty constructing two phase CCD's with such impurity regions not self-aligned to the gates, because misalignment in either direction produces potential "wells" or potential "barriers" which trap charge during transfer, as is well known in the art, discussed for example by Banghart et al. in COMPEL-The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Vol. 10, No. 4, 205-213, 1991. Also, the regions of overlap of the second conductive electrode strips over the first conductive electrode strips, as has been long practiced in the art, reduce the amount of light penetrating the electrode structure and introduce process dependent variability in the amount of light passed. In addition, all the methods thus far cited suffer increased topography as practiced, due to the overlap of electrodes, generally not desirable in semiconductor processing.
Virtual phase CCD's, as taught by Frye et al. in U.S. Pat. No. 4,047,215, Nichols et al. in U.S. Pat. No. 4,992,392, and by Hynecek in U.S. Pat. No. 4,229,752, have been employed to substantially accomplish self-alignment of the potential in the semiconductive substrate due to a direction biasing implant under the clocked electrode. In this technology, one set of physical electrodes is replaced by a heavily doped region near the surface of the semiconductive substrate. Such virtual phase electrodes are used to uniformly fix or pin the surface potential in a manner self-aligned to the adjacent physical gate electrode and to negate the effect of misalignment of direction biasing implants under the physical electrode. In addition to accomplishing self-alignment of implant and electrode, this technology also allows a large fraction of incident light to pass directly into the semiconductor substrate, and the absence of a second conductive electrode improves the device topography. However, the amount of charge that can be transferred in virtual phase CCD's is limited due to the inability to clock the potential of the pinned region. Also, the process taught by U.S. Pat. No. 4,229,752 requires diffusion of the implanted dopant out of an insulative material, a process difficult to control and producing lateral spreading of implant profiles, an effect also well known in the art to itself produce "wells" and "barriers" to charge transfer. Such diffusion out of an insulative material is also required by a similar method of fabrication of two phase CCDs taught by Tasch et al. in U.S. Pat. No. 4,167,017.
Anthony et al. in U.S. Pat. No. 3,927,468, Losee et al. in U.S. Pat. No. 4,613,402, and Hawkins et al. in U.S. Pat. No. 4,746,622 disclose methods of fabricating self-aligned two phase CCD's in which the charge transfer direction biasing implants are fully self-aligned to phase 1 and phase 2 electrodes, both of which can be clocked independently. Although the implants taught are self-aligned, CCD's fabricated by these method suffer some degree of implant induced potential "wells" and potential "barriers" due to the inherent necessity in these methods of implanting at least one direction biasing implant through the gate electrode. This implantation procedure requires a higher energy implantation in comparison to implantation through the insulative layer alone or directly into the semiconductive substrate which is well known in the art to result in lateral spreading or straggle of the implant in the semiconductive substrate, such straggle in turn inducing potential "wells" and "barriers", also known in the art. Again, the regions of overlap of the electrodes reduce the amount of light penetrating the electrode structure and introduce process dependent variability in the amount of light passed as well as well as additional topography.
Amelio et al., in U.S. Pat. No. 3,911,560, teaches a method to construct self-aligned two phase CCD's in which the charge transfer direction biasing implants are fully self-aligned to electrode phases, both of which are clocked, and which does not require implantation of a charge transfer direction biasing implant to be through a gate electrode. Therefore, this method in principal avoids the occurrence of potential "wells" and "barriers" as well as enabling all phases to be clocked. Because the implants are made directly into the substrate or through only a thin dielectric layer, lateral spread of the implanted species is restricted and slowly diffusing dopants such as arsenic may be employed, additionally avoiding the occurrence of potential "wells" and "barriers". However, the fabrication steps of connecting two adjacent gate electrodes electrically to form a single gate electrode, as taught by U.S. Pat. No. 3,911,560, are cumbersome and require relatively large amounts of space The resulting structure of the device is not conducive to optical transmission, and device topography is greatly increased. It is particularly difficult to provide small devices whose storage regions alone are implanted in a self aligned manner, because the wider of the electrode strips must be deposited first, in order to accommodate the overlapping structure of the second conductive electrode strips. Thus the implant which is self-aligned occurs preferably under the second phase, or smaller of the electrode strips, and is thereby associated with the transfer region.